The invention relates to a DRAM cell arrangement, i.e. a memory cell arrangement with dynamic random access, and to a method for its production.
The development of DRAM cell arrangements is focused on increasing the packing density. Currently, in DRAM arrangements, what are known as single-transistor memory cells are employed almost exclusively. A single-transistor memory cell contains a transistor and a capacitor. The information is stored in the capacitor in the form of an electrical charge representing a logical quantity of 0 or 1. By the actuation of the transistor via a word line, this information can be read out via a bit line. The transistor is usually connected between the bit line and the capacitor (for example, see DE 195 19 160). In the readout of the information, the charge on a first capacitor electrode of the capacitor, which electrode is connected to the transistor, determines the voltage at the bit line. A second capacitor electrode, which is not connected to the transistor, is kept constantly at half the operating voltage. A voltage signal which is formed by the difference of the voltage at the bit line and half the operating voltage corresponds to the information. The charge at the second capacitor electrode remains unused.
U.S. Pat. No. 4,630,088 incorporated herein teaches a DRAM cell arrangement in which a capacitor is connected between a bit line and a transistor. The charge of a capacitor electrode which is connected to the bit line is utilized for the formation of a voltage signal to which the information corresponds.
In T. Inaba, et al, "250 mV Bit-Line Swing Scheme for a 1V 4 Gb DRAM," 1995 Symposium on VLSI Circuits Digest of Technical Papers: pp. 99-100, a DRAM cell arrangement is proposed in which a transistor is connected to a first bit line and a capacitor is connected to a second bit line. A voltage signal to which the information corresponds is generated by the difference of the voltages of the two bit lines, and so in effect by the charges on the two capacitor electrodes. In the charging of the capacitors, the operating voltage is applied either at the first bit line or at the second bit line. At the respective other bit line, 0V is applied. The second bit line is arranged in a depression and serves as a capacitor electrode. The first bit line and the second bit line extend parallel to one another. Due to the utilization of both charges of the capacitor instead of one charge, and due to the described actuation of the bit lines in the charging of the capacitor, for the same strength of the voltage signal, a smaller operating voltage is necessary here than in the DRAM cell arrangements with only one bit line. A smaller operating voltage means less lost power and enables a higher packing density of the DRAM cell arrangement.
The patents DE 195 19 160 and DE 196 37 389 teach the creation of word lines of a DRAM cell arrangement in self-adjusted fashion, i.e. without the utilization of adjusting masks. For this purpose, parallel first trenches are created, which are narrowed by the depositing and etchback of material. Perpendicular to the first trenches, second trenches are created whose width conforms to the original width of the first trenches. The narrowed first trenches are accordingly narrower than the second trenches. Material is deposited and etched back to create the word lines, whereby word lines emerge, in self-adjusted fashion, which extend parallel to the second trenches and which surround transistors in annular fashion.
In Y. Nishioka et al, "Giga-Bit Scale DRAM Cell with New Simple Ru/(Ba, Sr)TiO.sub.3 /Ru Stacked Capacitors Using X-Ray Lithography", IEDM 95: p. 903, a DRAM cell arrangement is described in which a transistor is connected between a capacitor and a bit line. The capacitor is arranged over the transistor. Separate capacitor electrodes are provided with a capacitor dielectric, at which a capacitor plate adjoins.